Light emitting structure with integral reverse voltage protection

ABSTRACT

A light emitting structure having reverse voltage protection (RVP) is provided along with disclosure of a method for fabricating the light emitting structure. The light emitting structure includes a substrate having a first face, a second face, and a p-n junction formed within the substrate between a p-type layer and an n-type layer, wherein the p-type layer and the n-type layer are adapted as a RVP diode. A buffer layer is provided on the substrate, and a light emitting diode (LED) is fabricated on the buffer layer. The LED is then electrically coupled to the RVP diode in an anti-parallel diode pair (APDP) configuration.

RELATED APPLICATIONS

This application claims the benefit of provisional patent applicationSer. No. 61/227,630, filed Jul. 22, 2009, the disclosure of which ishereby incorporated herein by reference in its entirety. The applicationalso relates to provisional patent application Ser. No. 61/227,624,filed Jul. 22, 2009, and to utility patent application Ser. No.12/705,869 filed Feb. 15, 2010, both of which are hereby incorporatedherein by reference in their entireties.

FIELD OF THE DISCLOSURE

The present disclosure relates to a light emitting structure having areverse voltage protection diode that is dimensionally efficient andinexpensive to manufacture.

BACKGROUND OF THE DISCLOSURE

Semiconductor structures such as light emitting diodes (LEDs) aresusceptible to damage from accidental applications of reverse voltages.A reverse voltage condition can occur if an LED is inadvertently placedinto a circuit backwards. For example, someone may accidentally couple acathode of the LED to an anode pad of the circuit while coupling ananode of the LED to a cathode pad of the circuit. As a result, the LEDwill likely be damaged to a point of complete failure at the momentpower is applied to the LED.

Moreover, LEDs are susceptible to electrostatic discharge (ESD).Triboelectric effects can lead to a large potential difference across anelectrically insulating material. An ESD may occur if a large potentialdifference develops across a semiconductor device. A resultantshort-duration high-current pulse flowing through the semiconductordevice will likely damage the semiconductor device to a point ofcomplete failure. LEDs are particularly vulnerable in that a reversevoltage resulting from an ESD of only a few volts of reverse biaspotential difference is usually enough to damage an LED.

Prior art attempts to protect LEDs from accidental reverse voltageand/or ESD include coupling a cathode of an external diode to an anodeof an LED to be protected along with coupling a cathode of the LED to ananode of the external diode. In this configuration, a potentiallydestructive current resulting from an accidental reverse voltage or ESDwill harmlessly pass through the external diode while bypassing the LEDbeing protected. While external diodes do a good job of protecting LEDs,there are disadvantages in using external diodes. One disadvantage is anincreased manufacturing cost due to additional assembly processes thatare needed to add an external diode to an LED. Another disadvantage isan undesirable increase in package size needed to accommodate theexternal diode. This disadvantage is especially evident when it isdesirable to minimize the size of a reverse voltage protected LED. Forexample, an external diode used to protect an LED designed for a flipchip-type package would defeat the purpose of the flip chip-typepackage, which is to minimize the space taken up by the LED. Therefore,a need remains for an LED that preserves the smallest-size packageintended for the LED while including a reverse voltage protection (RVP)diode that is relatively inexpensive to add to the LED.

SUMMARY OF THE DISCLOSURE

The present disclosure describes the use of standard silicon technologyto fabricate a p-n junction into a substrate prior to fabricating alight emitting structure on top of the substrate. In this way, the p-njunction is integral with the light emitting structure and is usable toprotect the light emitting structure from reverse voltage events such asaccidental reverse voltage application and/or an electrostatic discharge(ESD). The combination of the p-n junction within the substrate of thelight emitting structure forms a light emitting diode (LED) that isintegral with a protective diode formed by the p-n junction. Since theprotective diode is integrally formed with the light emitting structure,the protective diode is relatively inexpensive to add to the LED, whileat the same time, it allows the manufacturer to preserve thesmallest-size package intended for the LED.

In particular, the present disclosure provides a gallium nitride (GaN)LED that is reverse voltage protected and well suited for flip chip-typepackaging. A process of manufacture for the GaN LED uses standardsilicon manufacturing processes to fabricate a p-n junction into asubstrate onto which the light emitting structure making up the GaN LEDis grown. The p-n junction may be fabricated into the substrate prior togrowing the light emitting structure of the GaN LED. The p-n junctioncan be formed by impurity diffusion or by ion implantation. A bufferlayer for reducing strain between the substrate and the light emittingstructure is formed on the substrate before the light emitting structureof the GaN LED is grown.

Fabrication of the light emitting structure of the GaN LED may beaccomplished using standard semiconductor fabrication techniques.However, the formation of electrical contacts for the light emittingstructure may include mesa or trench processing steps to access thedoped material within the substrate.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1A is a cross-section view of one embodiment of a light emittingstructure according to the present disclosure.

FIG. 1B is a symbolic representation of a anti-parallel diode pair(APDP) that is realized in the light emitting structure of FIG. 1A.

FIG. 2 is a cross-section view of another embodiment of a light emittingstructure, which includes grooves in the substrate for scattering lightin accordance with the present disclosure.

FIG. 3 is a flowchart of a method of manufacture for a light emittingstructure according to the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the disclosure andillustrate the best mode of practicing the disclosure. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

FIG. 1A provides a cross-section view of one embodiment of a lightemitting structure 10 according to the present disclosure. The lightemitting structure 10 includes a substrate 12 having a first face 14, asecond face 16, and a p-n junction 18 formed from a first substratelayer 20 that is adjacent to a second substrate layer 22. In thisparticular embodiment, it is preferred that the substrate be made ofsilicon. The first substrate layer 20 and the second substrate layer 22are adapted as a reverse voltage protection (RVP) diode 24 shownsymbolically in FIG. 1B. As depicted in FIG. 1A, the first substratelayer 20 is made of p-type silicon and the second substrate layer 22 ismade of n-type silicon. The p-n junction may be formed by bonding ann-type silicon wafer to a p-type silicon wafer. Alternately, the p-njunction may be formed by diffusing a p-type dopant into an n-typesilicon layer of the substrate.

The first face 14 of the substrate 12 may have a preferred orientationof crystalline structure in order to minimize crystal lattice mismatchesbetween the first face 14 of the substrate 12 and a layer that may begrown or deposited onto the first face 14 of the substrate 12. Forexample, the first face 14 of the substrate 12 may have a silicon (Si)crystal lattice that is preferably directed in a <111> plane in order tominimize the crystal lattice mismatch and hence mechanical strainbetween the substrate 12 and another layer deposited or grown on thefirst face 14. However, other planes of a Si crystal lattice may providea nucleation needed to minimize the crystal lattice mismatch between thesubstrate and another layer deposited or grown on the first face 14.

A buffer layer 26 is provided on the substrate 12. The buffer layer 26may be grown or deposited on the substrate 12. The buffer layer 26 maycomprise sub-layers of aluminum nitride (AlN) and various compounds ofaluminum gallium nitride (Al_(x)Ga_(1-x)N), wherein x is greater thanzero but less than or equal to one. Alternately, the substrate 12 maycomprise AlN. Further still, the substrate 12 may be made of a pluralityof layers of Al_(x)Ga_(1-x)N (0<x≦1).

A first doped layer 28 is provided on the buffer layer 26. The firstdoped layer 28 may be deposited or grown on the buffer layer 26.Preferably the first doped layer 28 is made of n-type gallium nitride(GaN). A multiple quantum well (MQW) structure layer 30 is grown ontothe first doped layer 28, and a second doped layer 32 is deposited ontothe MQW structure layer 30. The first doped layer 28, the MQW structurelayer 30, and the second doped layer 32 make up a light emitting diode(LED) 34 that is electrically coupled to the RVP diode 24 in ananti-parallel diode pair (APDP) configuration 36 as shown symbolicallyin FIG. 1B. The APDP configuration 36 of the present disclosureelectrically couples the cathode of the RVP diode 24 to the anode of theLED 34 and also electrically couples the cathode of the LED 34 to theanode of the RVP diode 24. The RVP diode 24 acts as a reverse voltageprotection device that electrically conducts a potentially damagingreverse voltage urged current to bypass the LED 34 if the reversevoltage across the LED 34 exceeds a predetermined voltage.

Turning attention back to FIG. 1A, a first electrical contact 38 isprovided on the second doped layer 32, a second electrical contact 40 isprovided on the first doped layer 28, a third electrical contact 42 isprovided onto the first face 14 of the substrate 12, and a fourthelectrical contact 44 is provided onto the second face 16 of thesubstrate 12. The APDP configuration 36 (FIG. 1B) is realized byelectrically coupling the first electrical contact 38 to the fourthelectrical contact 44 via a first conductor 46, and by electricallycoupling the second electrical contact 40 to the third electricalcontact 42 via a second conductor 48.

FIG. 2 depicts an alternate embodiment of the light emitting structure10 of FIG. 1. In this embodiment, the substrate 12 includes a pluralityof grooves 50 that are fabricated into the first face 14 of thesubstrate 12. The plurality of grooves 50 may be fabricated via etchingthe first face 14 of the substrate 12 using a wet chemistry etchant suchas potassium hydroxide (KOH) or by mechanical etching. The first face 14has a crystal lattice that is directed in the <100> plane and the eachof the plurality of grooves 50 has sidewalls 52 that are formed within<111> planes. The preferred shape for the plurality of grooves 50 is aV, as shown in FIG. 2. However, other shapes for the plurality ofgrooves 50 are possible. Moreover, the first face 14 may haveorientations other than the preferred <100> plane orientation. Furtherstill, a minimum channel width of the each of the plurality of grooves50 is two to ten times greater than a given wavelength of a lightemission of the LED 34.

The plurality of grooves 50 scatters the light produced by the LED 34with an efficiency that is significant enough to reduce a need forexternal reflective surfaces. Thus, the light emitting structure 10 issuitable for flip chip packaging. For example, as shown in FIG. 2, thelight emitting structure 10 may be mounted on a flip chip-sized LEDsub-mount 54. The LED sub-mount 54 preferably has a metalized andpatterned surface that includes metal contacts 56.

FIG. 3 depicts a method of fabricating the light emitting structure 10(FIGS. 1A and 2). An embodiment of the disclosure uses Si as a basematerial making up the substrate 12. The method may begin by providingthe substrate 12 having the first face 14 and the second face 16,wherein the plurality of grooves 50 (FIG. 2) are etched into the firstface 14 of the substrate 12 (step 100). Next, the p-n junction 18 isformed within the substrate 12 between the first substrate layer 20 andthe second substrate layer 22 (step 102). The first substrate layer 20and the second substrate layer 22 are adapted to be the RVP diode 24(FIG. 1B). Various methods for forming the p-n junction 18 of the RVPdiode 24 are known in the prior art. For example, a p-type dopant can bediffused into an n-type layer to produce the first substrate layer 20,and thus the p-n junction 18. Alternately, the first substrate layer 20can be grown on the second substrate layer 22 (or vice versa). Furtherstill, the p-n junction 18 can be formed by bonding an n-type wafer to ap-type wafer. Step 100 and step 102 may be exchanged, but it isgenerally preferable for the plurality of grooves 50 to be etched beforethe p-n junction 18 is formed.

Another step includes providing the buffer layer 26 onto the first face14 of the substrate 12 (step 104). The buffer layer 26 may be grown ordeposited on the substrate 12. The buffer layer 26 may comprisesub-layers of AlN and various compounds of Al_(x)Ga_(1-x)N, wherein x isgreater than zero but less than or equal to one. Alternately, the bufferlayer 26 may comprise only AlN. Further still, the buffer layer 26 maybe made of a plurality of layers made of Al_(x)Ga_(1-x)N (0<x≦1).

Other steps include fabricating the LED 34 (FIG. 1B). The fabrication ofthe LED 34 begins by providing the first doped layer 28 on the bufferlayer 26 (step 106). Preferably, the step 106 is accomplished bydepositing or growing the first doped layer 28 on the buffer layer 26.It is also preferable for the first doped layer 28 to be made of n-typedoped GaN.

In order to allow the light emitting structure to emit lightefficiently, a step of fabricating the MQW structure layer 30 onto thefirst doped layer 28 is performed using standard MQW fabricationtechnology (step 108). Another step completes the LED 34 by providingthe second doped layer 32 onto the MQW structure layer 30 (step 110).The step 110 providing the second doped layer 32 is preferablyaccomplished by depositing or growing p-type doped GaN onto the MQWstructure layer 30.

Next, a series of steps are performed to make electrical connectionsbetween the RVP diode 24 and the LED 34. These steps may begin byproviding the first electrical contact 38 on the second doped layer 32(step 112). The first electrical contact 38 is preferably made of amaterial that is the same type as the second doped layer 32. Forexample, if the second doped layer 32 is made of n-type material, thenthe first electrical contact 38 should also be made of n-type material.A next step includes etching through the second doped layer 32 and theMQW structure layer 30 to expose a section of the first doped layer 28(step 114). Another step involves providing the second electricalcontact 40 onto the first doped layer 28 (step 116). Yet another stepincludes etching through the first doped layer 28 and the buffer layer26 to expose a section of the first face 14 of the substrate 12 (step118). A further step includes providing the third electrical contact 42on the first face 14 of the substrate 12 (step 120). Another stepinvolves providing the fourth electrical contact 44 onto the second face16 of the substrate 12 (step 122).

Other steps involve making electrical connections such that the LED 34and RVP diode 24 make up the APDP configuration 36. One of these stepsinvolves coupling electrically the first electrical contact 38 to thefourth electrical contact 44 via the first conductor 46 (step 124).Another step includes coupling electrically the second electricalcontact 40 to the third electrical contact 42 via the second conductor48 (step 126).

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

1. A light emitting structure having reverse voltage protection (RVP),the light emitting structure comprising: a substrate having a firstface, a second face, and a p-n junction formed within the substratebetween a p-type layer and an n-type layer, wherein the p-type layer andthe n-type layer are adapted as a RVP diode; a buffer layer provided onthe substrate; and a light emitting diode (LED) fabricated onto thebuffer layer, wherein the LED is electrically coupled to the RVP diodein an anti-parallel diode pair (APDP) configuration.
 2. The lightemitting structure of claim 1 wherein the substrate comprises silicon(Si).
 3. The light emitting structure of claim 1 wherein the LEDcomprises: a first doped layer provided on the buffer layer; a multiplequantum well (MQW) structure layer fabricated on the first doped layer;and a second doped layer provided on the MQW structure layer.
 4. Thelight emitting structure of claim 3 wherein the first doped layer ismade of n-doped gallium nitride (GaN).
 5. The light emitting structureof claim 3 wherein the second doped layer is made of p-doped GaN.
 6. Thelight emitting structure of claim 1 wherein the buffer layer isdeposited or grown on the first face of the substrate.
 7. The lightemitting structure of claim 1 wherein the buffer layer comprisessub-layers of aluminum nitride (AlN) and aluminum gallium nitride(Al_(x)Ga_(1-x)N) (0<x≦1).
 8. The light emitting structure of claim 1wherein the buffer layer is made of AlN.
 9. The light emitting structureof claim 1 wherein the buffer layer is made of Al_(x)Ga_(1-x)N (0<x≦1).10. The light emitting structure of claim 1 wherein the buffer layercomprises a plurality of layers made of Al_(x)Ga_(1-x)N (0<x≦1).
 11. Thelight emitting structure of claim 1 wherein the first face of thesubstrate is a <111> plane.
 12. The light emitting structure of claim 1wherein the first face of the substrate comprises a <100> plane having aplurality of grooves therein, wherein each of the plurality of groovesinclude sidewalls that are <111> planes.
 13. The light emittingstructure of claim 12 wherein a minimum channel width of the each of theplurality of grooves is two to ten times greater than a given wavelengthof a light emission of the LED.
 14. A method of fabricating a lightemitting structure, the method comprising: providing a silicon (Si)substrate having a first face, a second face, and a p-n junction formedwithin the substrate between a p-type layer and an n-type layer, whereinthe p-type layer and the n-type layer are adapted as an RVP diode;depositing or growing a buffer layer onto the first face of thesubstrate; fabricating a LED via steps comprising: depositing or growinga first doped layer onto the buffer layer; fabricating an MQW structurelayer on the first doped layer; depositing or growing a second dopedlayer onto the MQW structure layer; providing a first electrical contacton the second doped layer; etching through the second doped layer andthe MQW structure layer to expose the first doped layer; providing asecond electrical contact on the first doped layer; etching through thefirst doped layer and the buffer layer to expose the first face of thesubstrate; providing a third electrical contact on the first face of thesubstrate; providing a fourth electrical contact on the second face ofthe substrate; and coupling electrically the first electrical contact tothe fourth electrical contact and the second electrical contact to thethird electrical contact such that the LED and RVP diode make up an APDPconfiguration.
 15. The method of claim 14 wherein providing thesubstrate with the p-n junction comprises diffusing a p-type dopant intoan n-type silicon (Si) layer of the substrate.
 16. The method of claim14 wherein providing the substrate with the p-n junction comprisesbonding an n-type Si wafer to a p-type Si wafer.
 17. The method of claim14 further including producing a plurality of grooves in the first faceof the substrate before depositing or growing the buffer layer onto thefirst face of the substrate.
 18. The method of claim 17 whereinproducing the plurality of grooves is accomplished via etching the firstface of the substrate using a wet chemistry etchant.
 19. The method ofclaim 18 wherein the wet chemistry etchant is potassium hydroxide (KOH).20. The method of claim 17 wherein producing the plurality of grooves isaccomplished via mechanical etching.
 21. The method of claim 14 furtherincluding mounting the light emitting structure onto an LED sub-mountvia adhering the fourth electrical contact of the light emittingstructure to the LED sub-mount.